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Rev 1; 10/08
Dual-Channel, I2C Adjustable Sink/Source Current DAC
General Description
The DS4412 contains two I2C adjustable-current DACs that are each capable of sinking or sourcing current. Each output has 15 sink and 15 source settings that are programmed by I2C interface. The full-scale range and step size of each output is determined by an external resistor that can adjust the output current over a 4:1 range. The output pins, OUT0 and OUT1, power-up in a highimpedance state.
Features
Two Current DACs Full-Scale Current 500A to 2mA Full-Scale Range for Each DAC Determined by External Resistors 15 Settings Each for Sink and Source Modes I2C-Compatible Serial Interface Low Cost Small Package (8-Pin SOP) -40C to +85C Temperature Range 2.7V to 5.5V Operation
DS4412
Applications
Power-Supply Adjustment Power-Supply Margining Adjustable Current Sink or Source
Ordering Information Pin Configuration
TOP VIEW +
SDA 1 SCL FS1 GND 2 3 4 8 7 VCC OUT1 OUT0 FS0
PART DS4412U+ DS4412U+T&R
TEMP RANGE -40C to +85C -40C to +85C
PIN-PACKAGE 8 SOP 8 SOP
+Denotes a lead-free/RoHS-compliant package. T&R = Tape and reel.
DS4412
6 5
SOP
Typical Operating Circuit
VCC VOUT0 VOUT1 4.7k 4.7k SDA SCL VCC DC-DC CONVERTER OUT R0A FB R0B DC-DC CONVERTER FB R1B OUT R1A
DS4412
GND
OUT0 OUT1
FS0 RFS0
FS1 RFS1
________________________________________________________________ Maxim Integrated Products
1
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Dual-Channel, I2C Adjustable Sink/Source Current DAC DS4412
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VCC, SDA, and SCL Relative to Ground.............................................-0.5V to +6.0V Voltage Range on OUT0, OUT1 Relative to Ground ................-0.5V to (VCC + 0.5V) (Not to exceed 6.0V.) Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-55C to +125C Soldering Temperature .....................................Refer to IPC/JEDEC J-STD-020 Specification
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40C to +85C)
PARAMETER Supply Voltage Input Logic 1 (SDA, SCL) Input Logic 0 (SDA, SCL) SYMBOL VCC VIH VIL (Note 1) CONDITIONS MIN 2.7 0.7 x VCC -0.3 TYP MAX 5.5 VCC + 0.3 0.3 x VCC UNITS V V V
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40C to +85C.)
PARAMETER Supply Current Input Leakage (SDA, SCL) Output Leakage (SDA) Output Current Low (SDA) RFS Voltage I/O Capacitance SYMBOL ICC I IL IL I OL VRFS CI/O VOL = 0.4V VOL = 0.6V 3 6 0.607 10 VCC = 5.5V CONDITIONS VCC = 5.5V (Note 2) MIN TYP MAX 500 1 1 UNITS A A A mA V pF
OUTPUT CURRENT CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40C to +85C.)
PARAMETER Output Voltage for Sinking Output Voltage for Sourcing Current Full-Scale Sink Output Current Full-Scale Source Output Current Output-Current Full-Scale Accuracy Output-Current Temperature Coefficient SYMBOL VOUT:SINK VOUT:SOURCE IOUT:SINK IOUT:SOURCE I OUT:FS CONDITIONS VCC > V OUT:SINK (Note 3) (Note 3) (Note 3) (Note 3) +25C, VCC = 4.0V; using 0.1% RFS resistor (Note 4) VOUT0 = VOUT1 = 1.2V (Note 5) 75 MIN 0.5 0 0.5 -2.0 TYP MAX 3.5 VCC 0.75 2.0 -0.5 6 UNITS V V mA mA %
I OUT:TC
ppm/C
2
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Dual-Channel, I2C Adjustable Sink/Source Current DAC
OUTPUT CURRENT CHARACTERISTICS (continued)
(VCC = +2.7V to +5.5V, TA = -40C to +85C.)
PARAMETER Output-Current Variation due to Power-Supply Change Output-Current Variation due to Output Voltage Change Output Leakage Current at Zero Current Setting Output-Current Differential Linearity Output-Current Integral Linearity I ZERO DNL INL (Note 6) (Note 7) SYMBOL DC source DC sink DC source, V OUT measured at 1.2V DC sink, VOUT measured at 1.2V -1 CONDITIONS MIN TYP +0.36 +0.12 -0.02 +0.12 +1 0.5 1 MAX UNITS %/V %/V A LSB LSB
DS4412
I2C AC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40C to +85C.)
PARAMETER SCL Clock Frequency Bus Free Time Between STOP and START Conditions Hold Time (Repeated) START Condition Low Period of SCL High Period of SCL Data Hold Time Data Setup Time START Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Setup Time SDA and SCL Capacitive Loading SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tDH:DAT tSU:DAT tSU:STA tR tF tSU:STO CB (Note 9) (Note 9) (Note 9) (Note 8) CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0 100 0.6 20 + 0.1CB 20 + 0.1CB 0.6 400 300 300 0.9 TYP MAX 400 UNITS kHz s s s s s ns s ns ns s pF
Note 1: All voltages with respect to ground, currents entering the IC are specified positive and currents exiting the IC are negative. Note 2: Supply current specified with all outputs set to zero current setting with all inputs driven to well-defined logic levels. SDA and SCL are connected to VCC. Excludes current through RFS resistors (IRFS). Total current includes ICC + 2.5 x (IRFS0 + IRFS0). Note 3: The output voltage range must be satisfied to ensure the device meets its accuracy and linearity specifications. Note 4: Input resistors RFS must be between 2.25k and 9.0k to ensure the device meets its accuracy and linearity specifications. Note 5: Temperature drift excludes drift caused by external resistor. Note 6: Differential linearity is defined as the difference between the expected incremental current increase with respect to position and the actual increase. The expected incremental increase is the full-scale range divided by 15. Note 7: Integral linearity is defined as the difference between the expected value as a function of the setting and the actual value. The expected value is a straight line between the zero and the full-scale values proportional to the setting. Note 8: Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard-mode timing. Note 9: CB--total capacitance of one bus line in pF.
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Dual-Channel, I2C Adjustable Sink/Source Current DAC DS4412
Pin Description
NAME SDA SCL FS1 FS0 GND OUT0 OUT1 VCC PIN 1 2 3 5 4 6 7 8 I2C Serial Data. Input/output for I2C data. I2C Serial Clock. Input for I2C clock. Full-Scale Calibration Inputs. A resistor to ground on these pins determines the full-scale current for each output. FS0 controls OUT0, FS1 controls OUT1. Ground Current Outputs. Sinks or sources the current determined by the register settings and the resistance connected to FS0 and FS1. Power Supply FUNCTION
Typical Operating Characteristics
(Applies to OUT0 and OUT1. VCC = 2.7V to 5.0V, SDA = SCL = VCC, TA = +25C, and no loads on OUT0, OUT1, FS0, or FS1, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
DS4412 toc01
SUPPLY CURRENT vs. TEMPERATURE
DS4412 toc02
VOLTCO (SOURCE)
2.2k LOAD ON FS0 AND FS1 2.4
DS4412 toc03
0.5
0.35 VCC = 5.0V 0.30 SUPPLY CURRENT (mA) 0.25 0.20 0.15 0.10 0.05 DOES NOT INCLUDE CURRENT DRAWN BY RESISTORS CONNECTED TO FS0 AND FS1. VCC = 3.3V VCC = 2.7V
2.5
0.4 SUPPLY CURRENT (mA) DOES NOT INCLUDE CURRENT DRAWN BY RESISTORS CONNECTED TO FS0 AND FS1. 0.3
IOUT (mA)
2.3
0.2
2.2
0.1
2.1
0 2.7 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V)
0 -40 -20 0 20 40 60 80 TEMPERATURE (C)
2.0 0 1 2 VOUT (V) 3 4 5
VOLTCO (SINK)
DS4412 toc04
TEMPERATURE COEFFICIENT vs. SETTING (SOURCE)
TEMPERATURE COEFFICIENT (C/ppm) TEMPERATURE COEFFICIENT (C/ppm) 70 60 50 40 30 20 10 0 0 5 10 15 SETTING (DEC) RANGE FOR THE 0.5mA TO 2.0mA CURRENT-SOURCE RANGE. +25C TO +85C +25C TO -40C
DS4412 toc05
TEMPERATURE COEFFICIENT vs. SETTING (SINK)
70 60 50 40 30 20 10 0 0 5 10 15 SETTING (DEC) +25C TO +85C RANGE FOR THE 0.5mA TO 2.0mA CURRENT-SOURCE RANGE. +25C TO -40C
DS4412 toc06
-2.0 2.2k LOAD ON FS0 AND FS1 -2.1
80
80
IOUT (mA)
-2.2
-2.3
-2.4
-2.5 0 1 2 VOUT (V) 3 4
4
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Dual-Channel, I2C Adjustable Sink/Source Current DAC
Typical Operating Characteristics (continued)
(Applies to OUT0 and OUT1. VCC = 2.7V to 5.0V, SDA = SCL = VCC, TA = +25C, and no loads on OUT0, OUT1, FS0, or FS1, unless otherwise noted.)
INTEGRAL LINEARITY
DS4412 toc07
DS4412
DIFFERENTIAL LINEARITY
0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 RANGE FOR THE 0.5mA TO 2.0mA CURRENT SOURCE AND SINK RANGE
DS4412 toc08
1.0000 0.7500 0.5000 INL (LSB) 0.2500 0.0000 -0.2500 -0.5000 -0.7500 -1.0000 0 5 10 RANGE FOR THE 0.5mA TO 2.0mA CURRENT SOURCE AND SINK RANGE
1.0
15
0
5
10
15
SETTING (DEC)
SETTING (DEC)
Block Diagram
SDA SCL
VCC
I2C-COMPATIBLE SERIAL INTERFACE
VCC F8h SOURCE OR SINK MODE GND CURRENT DAC0 F9h 15 POSITIONS EACH FOR SINK AND SOURCE MODE
DS4412
CURRENT DAC1
FS0 RFS0
OUT0
FS1 RFS1
OUT1
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Dual-Channel, I2C Adjustable Sink/Source Current DAC DS4412
Detailed Description
The DS4412 contains two I 2 C adjustable-current sources that are each capable of sinking and sourcing current. Each output, OUT0 and OUT1, has 15 sink and 15 source settings that are programmed through the I2C interface. The full-scale ranges and corresponding step sizes of the outputs are determined by external resistors, connected to pins FS0 and FS1, which can adjust the output currents over a 4:1 range. The formula to determine the positive and negative full-scale current ranges for each of the four outputs is given by: RFS = (VRFS / IFS) x (15 / 1.974) where V RFS is the R FS voltage (see DC Electrical Characteristics), and RFS is the external resistor value. On power-up, the DS4412 outputs zero current. This is done to prevent it from sinking or sourcing an incorrect current before the system host controller has had a chance to modify the device's setting. As a source for biasing instrumentation or other circuits, the DS4412 provides a simple and inexpensive current source with an I2C interface for control. The adjustable full-scale range allows the application to get the most out of its 4-bit sink or source resolution. When used in adjustable power-supply applications (see Typical Operating Circuit), the DS4412 does not affect the initial power-up supply voltage because it defaults to providing zero output current on power-up. As it sources or sinks current into the feedback voltage node, it changes the amount of output voltage required by the regulator to reach its steady state operating point. Using the external resistor, RFS, to set the output current range, the DS4412 provides some flexibility for adjusting the range over which the power supply can be controlled or margined.
Memory Organization
The DS4412's current sources are controlled by writing to the memory addresses in Table 1.
Table 1. Memory Addresses
MEMORY ADDRESS (HEXADECIMAL) 0xF8 0xF9 CURRENT SOURCE OUT0 OUT1
The format of each output control register is given by:
MSB S X X X D3 D2 D1 LSB D0
Where:
BIT NAME FUNCTION Determines if DAC sources or sinks current. For sink S = 0, for source S = 1. POWER-ON DEFAULT 0b XXX
S X
Sign Bit
DX
Reserved Reserved. 4-Bit Data Word Controlling DAC Output. Setting 0000b Data outputs zero current regardless of the state of the sign bit.
0000b
Example: RFS0 = 4.8k and register 0xF8h is written to a value of 0x8Ah. Calculate the output current. IFS = (0.607V / 4.8k) x (15 / 1.974) = 949.85A The MSB of the output register is 1, so the output is sourcing the value corresponding to position Ah (10 decimal). The magnitude of the output current is equal to: 949.85A x (10 / 15) = 633.23A
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Dual-Channel, I2C Adjustable Sink/Source Current DAC
I2C Serial Interface Description
I2C Slave Address The DS4412's slave address is 90h. I2C Definitions
The following terminology is commonly used to describe I2C data transfers: Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses and START and STOP conditions. Slave Devices: Slave devices send and receive data at the master's request. Bus Idle or Not Busy: Time between STOP and START conditions when both SDA and SCL are inactive and in their logic-high states. When the bus is idle it often initiates a low-power mode for slave devices. START Condition: A START condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a START condition. See Figure 1 for applicable timing. STOP Condition: A STOP condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a STOP condition. See Figure 1 for applicable timing. Repeated START Condition: The master can use a repeated START condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated START condition is issued identically to a normal START condition. See Figure 1 for applicable timing. Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL, plus the setup and hold time requirements (Figure 1). Data is shifted into the device during the rising edge of the SCL. Bit Read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time (Figure 1) before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses, including when it is reading bits from the slave. Acknowledgement (ACK and NACK): An Acknowledgement (ACK) or Not Acknowledge (NACK) is always the ninth bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the ninth bit. A device performs a NACK by transmitting a one during the ninth bit. Timing for the ACK and NACK is identical to all other bit writes (Figure 2). An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a
DS4412
SDA tBUF tF tLOW SCL tHD:STA tSP
tHIGH tHD:STA tR tHD:DAT STOP START tSU:DAT REPEATED START
tSU:STA
tSU:STO
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
Figure 1. I2C Timing Diagram
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Dual-Channel, I2C Adjustable Sink/Source Current DAC DS4412
TYPICAL I2C WRITE TRANSACTION MSB START 1 0 0 1 0 0 0 LSB R/W SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK STOP
SLAVE ADDRESS
READ/ WRITE
REGISTER/MEMORY ADDRESS
DATA
EXAMPLE I2C TRANSACTIONS 90h A) SINGLE BYTE WRITE -WRITE RESISTOR F9h TO 00h B) SINGLE BYTE READ -READ RESISTOR F8h F9h SLAVE 0 0 0 0 0 0 0 0 ACK SLAVE ACK 90h REPEATED START 1 0 0 1 0 0 0 1 SLAVE ACK STOP
START 1 0 0 1 0 0 0 0 SLAVE 1 1 1 1 1 0 0 1 ACK 90h F8h
DATA MASTER NACK STOP
START 1 0 0 1 0 0 0 0 SLAVE 1 1 1 1 1 0 0 0 SLAVE ACK ACK
Figure 2. I2C Communication Examples
read sequence or as an indication that the device is not receiving data. Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit-write definition, and the acknowledgement is read using the bit-read definition. Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminated communication so the slave will return control of SDA to the master. Slave Address Byte: Each slave on the I2C bus responds to a slave address byte sent immediately following a START condition. The slave address byte contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. The DS4412's slave address is 90h.
When the R/W bit is 0 (such as in 90h), the master is indicating it will write data to the slave. If R/W = 1 (91h in this case), the master is indicating it wants to read from the slave. If an incorrect slave address is written, the DS4412 assumes the master is communicating with another I2C device and ignores the communication until the next START condition is sent. Memory Address: During an I2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte.
I2C Communication Writing to a Slave: The master must generate a START condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a STOP condition. Remember that the master must read the slave's acknowledgement during all byte-write operations. Reading from a Slave: To read from the slave, the master generates a START condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a STOP condition.
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Dual-Channel, I2C Adjustable Sink/Source Current DAC
Applications Information
Example Calculation for an Adjustable Power Supply
In this example, the Typical Operating Circuit is used as a base to create Figure 3, a 2.0V voltage supply with 20% margin. The adjustable power supply has a DC-DC converter output voltage, VOUT, of 2.0V and a DC-DC converter feedback voltage, VFB, of 0.8V. To determine the relationship of R0A and R0B, we start with the equation: VFB = R 0B x VOUT R 0 A + R 0B And IR0 A = VOUT - VFB R 0A Where: IR0B = VFB R 0B
DS4412
To create a 20% margin in the supply voltage, the value of VOUT is set to 2.4V. With these values in place, R0B is calculated to be 267, and R0A is calculated to be 400. The current DAC in this configuration allows the output voltage to be moved linearly from 1.6V to 2.4V using 15 settings. This corresponds to a resolution of 25.8mV/step.
Substituting VFB = 0.8V and VOUT = 2.0V, the relationship between R0A and R0B is determined to be: R0A = 1.5 x R0B IOUT0 is chosen to be 1mA (midrange source/sink current for the DS4412). Summing the currents into the feedback node, we have the following I OUT0 = IR0B - IR0 A
VCC Decoupling To achieve the best results when using the DS4412, decouple the power supply with a 0.01F or 0.1F capacitor. Use a high-quality ceramic surface-mount capacitor if possible. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate highfrequency response for decoupling applications.
VCC
VOUT = 2.0V
4.7k
4.7k SDA SCL
VCC DC-DC CONVERTER
OUT IR0A FB IR0B R0B = 267 R0A = 400 VFB = 0.8V
DS4412
GND
OUT0
FS0 RFS0 = 4.612k IOUT0
Figure 3. Example Application Circuit
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 8 SOP PACKAGE CODE U8+1 DOCUMENT NO. 21-0036 9
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Dual-Channel, I2C Adjustable Sink/Source Current DAC DS4412
Revision History
REVISION NUMBER 0 1 REVISION DATE 9/07 10/08 Initial release. Added the I/O capacitance (CI/O) parameter to the DC Electrical Characteristics table. DESCRIPTION PAGES CHANGED -- 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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